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? semiconductor components industries, llc, 2015 november, 2015 ? rev. 4 1 publication order number: NCP81111/d NCP81111 3 phase vr12.5-6 high speed digital controller with svid and i 2 c interfaces for 5 mhz desktop, notebook cpu applications the NCP81111 is a high performance digital single output three phase vr12.5?6 compatible buck solution optimized to operate at frequencies up to 5 mhz for intel cpu applications. the NCP81111 and can also work as a general purpose i 2 c controlled multiphase voltage regulator. the NCP81111 is designed to s upport the ncp81163 digital phase doubler ic which expands the capability of the part to 6 phases for high current handling. the controller includes true differential voltage sensing, differential current sensing, digital input voltage feed?forward, dac feed forward, and adaptive voltage positioning. these features combine to provide an accurately regulated dynamic voltage system. the control system makes use of digital constant on time modulation and is combined with an analog and digital current sensing system. this system provides the fastest initial response to dynamic load events to reduced system cost. on board user programmable memory is included for configuring the controller?s parameters. user programmable voltage and droop compensation is internally integrated to minimize the total board space used. the NCP81111 is optimized for use with drmos. features ? meets intel ? ?s vr12.5 specifications ? on board eeprom for user configuration ? high performance digital architecture ? dynamic reference injection ? fully differential voltage current sense amplifiers ? ?lossless? dcr current sensing for current balancing ? thermally compensated inductor current sensing for droop ? user adjustable internal compensation ? switching frequency range of 250 khz ? 5.0 mhz ? input voltage feed?forward ? startup into pre?charged loads ? power saving phase shedding ? supports lower power operation in ps3 ? this is a pb?free device applications ? desktop, notebook processors, and general purpose i 2 c controlled multiphase regulators. marking diagram www. onsemi.com qfn32 case 485ce 32 1 NCP81111 zzrr awlyyww 1 NCP81111 = specific device code zz = configuration option rr = revision number a = assembly location wl = wafer lot yy = year ww = work week = pb?free package device* package shipping ? ordering information NCP81111mndftxg qfn32 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. (note: microdot may be in either location) *zz = configurable option, please contact sales fo r additional information. NCP81111mnzztxg qfn32 (pb?free) 2500 / tape & reel
NCP81111 www. onsemi.com 2 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 910111213 15 14 25 32 31 30 29 28 26 27 sda scl en test3/i2caddr0 vff vdig vccd vcca csn3 csp3 test1 test2/i2caddr1 csp1 csn1 csp2 csn2 vr_hot# sdio alert# sclk vr_rdy t_sense vsn vsp vccp pwm1 smod1 drvon pwm2 smod2 pwm3 smod3 figure 1. pinout diagram gnd
NCP81111 www. onsemi.com 3 csp1 csn1 6bit flash csp csn csout<5:0> phase mux + csp1 + csp2 + csp3 ? csn1 ? csn2 ? csn3 csp csn ton control freq setting csout ton1<> ton2<> ton3<> psx state vff_out<> csp2 csn2 uvlo vcca uvlo vdig csp3 digital integrator v1p3 diffout ioffset gain<> stop dac zcd compare csp1 csn1 zcd_threshold<> zdc1 high speed programmable compensator comp diffout compensation settings<> vfb ? + dac stop control v_threshold<> comp stop atod vff monitor vff vff_out<> ramp generator ramp current<> ramp cap<> ramp reset voltage <> phase count<> ramp ramp_go pwm control trigger pwm_go1 pwm_go2 pwm_go3 faults psx state ramp_go smod1 smod2 smod3 zcd1 phase count<> 5us blanking uvp monitor diffout 0.85v uvp dual dac vid<> ov_threshold<> dac ov_trshld 3v agnd ovp comparator ov_trshld vsp vsn ovp av iout gain control csp csn iout_p iout_n gain<> av droop gain control csp csn droop_p droop_n gain<> 10bit atod in_p in_n out<9:0> nonvolatile memory digital interface sda sclk settings analog monitoring fault status drvon vr_rdy vrhot# scl en alert# sdio thermal compensation temp_control<> csp csn thermal compensation temp_control<> csp csn thermal compensation temp_control<> csp csn csn3 phase mux +vsp +t_sense iout_p ? vsn ?t_sense iout_n aout_p aout_n current limit current summing amp + csp1 + csp2 + csp3 ? csn1 ? csn2 ? csn3 csp csn iout current summing amp + csp1 + csp2 + csp3 ? csn1 ? csn2 ? csn3 csp csn droop current summing amp + csp1 + csp2 + csp3 ? csn1 ? csn2 ? csn3 csp csn 100mhz error amp vp vn comp summing amp + vsp ? vsn ? dac + gnd + v1p3 diffout + droop_p ? droop_n ton timer pwm_go pwm ton<10:0> clk_800mhz ton timer pwm_go pwm ton<10:0> clk_800mhz ton timer pwm_go pwm ton<10:0> clk_800mhz dac current limit csp csn current limit<> ocp pwm1 pwm2 pwm3 v1 1.3vdc 0 5ns ramp comparator ramp comp trigger figure 2. block diagram
NCP81111 www. onsemi.com 4 pin list description pin no. symbol description 1 sda serial data configuration port 2 scl serial clock configuration port 3 en logic input. logic high enables output. 4 test3/i2ccadr0 debug and monitor port / i 2 c programming address offset 0 5 vff input voltage monitor 6 vdig digital power filter pin. internally regulated 7 vccd 5v digital vcc 8 vcca 5v analog vcc 9 vccp 5v driver vcc 10 pwm1 phase 1 pwm output. 11 smod1 low side fet enable signal 12 dron gate driver enable 13 pwm2 phase 2 pwm output 14 smod2 pwm 2 low side fet enable signal 15 pwm3 phase 3 pwm output 16 smod3 pwm3 low side fet enable signal 17 csn3 inverting input to current balance sense amplifier for phase 2 18 csp3 non?inverting input to current balance sense amplifier for phase 2 19 csn2 inverting input to current balance sense amplifier for phase 2 20 csp2 non?inverting input to current balance sense amplifier for phase 2 21 csn1 inverting input to current balance sense amplifier for phase 1 22 csp1 non?inverting input to current balance sense amplifier for phase 1 23 test2/addr1 monitor port / i 2 c programming address offset 1 24 test1 debug and monitor port 25 vsp non?inverting input to the core differential remote sense amplifier. 26 vsn inverting input to the core differential remote sense amplifier. 27 t_sense temp sense for the single phase converter 28 vr_hot# thermal logic output for over temperature. 29 vr_rdy open drain output. high indicates that the core output is regulating. 30 sclk serial vid clock. 31 alert# serial vid alert#. 32 sdio serial vid data interface. flag gnd power supply return ( qfn flag )
NCP81111 www. onsemi.com 5 figure 3. three phase application control circuit r2 0.0 r161 1.0k r162 130 c83 .015uf u6 NCP81111 scl 2 en 3 vff 5 vdig 6 vccd 7 vcca 8 pwm1 10 vccp 9 test3/i2caddr0 4 smod3 16 csn3 17 csp3 18 csp2 20 sdio 32 alert# 31 sclk 30 test1 24 test2/addr1 23 csp1 22 csn1 21 csn2 19 pwm3 15 smod1 11 drvon 12 vsp 25 vsn 26 vr_rdy 29 vr_hot# 28 sda 1 pwm2 13 t_sense 27 smod2 14 flag 33 c87 100pf rt22 220k r9 14.0k r4 0.0 r155 130 r12 49.9 r24 10.0 r156 54.9 c92 dnp j100 c80 .015uf c84 0.01uf c86 100pf r40 1.0k c82 0.01uf c85 .015uf r3 0.0 c222 10uf j94 c88 100pf r45 1 j92 r22 10.0 c51 1000pf c94 dnp r10 14.0k r157 75.0 r48 100 j13 1 2 c89 0.01uf r23 10.0 j99 j104 j131 usb?i2c_comm_module gnd input1 scl sca +5v j29 r34 100 jp5 etch 1 2 j27 c93 dnp r27 14.0k v_1p05_vccp agnd agnd agnd agnd agnd agnd agnd agnd pwm3 pwm2 pwm1 vss_sense smod1 sclk sdio vdc csn1 vccu vcc_sense vsn vsp csp3 csn3 csp2 csn2 csp1 vr_hot smod3 smod2 alert dron vr_rdy enable v5_cont sda scl vr_rdy enable vff alert_vr sclk sdio scl sda r46 0k place near j92 an j93 place by phase 1 inductor vsense r47 0k j95 j93 qfn 32, 5x5mm, 0p5 figure 4. three phase applications power stage circuit pwm2 gl2 pwm3 gl3 place close to drmos pins ncp5338 u3 vin 11 vin 12 vin 13 vin 14 vswh 15 pgnd 16 pgnd 17 pgnd 18 pgnd 19 pgnd 20 vswh 31 vswh 32 vswh 33 vswh 34 vswh 35 gl 36 cgnd 37 disb# 39 pwm 40 zcd_en# 1 vcin 2 nc 3 boot 4 gh 6 phase 7 vin 9 vin 10 pgnd 21 pgnd 22 pgnd 23 pgnd 24 pgnd 25 pgnd 26 pgnd 27 pgnd 28 vswh 29 vswh 30 cgnd 5 cgnd 41 vin 42 vswh 43 vin 8 thwn 38 gh3 j134 r19 0.00 j119 c269 1uf c52 4.7uf r20 1.00 place caps close to drmos pins on top place close to drmos pins csn3 smod3 sw3 vccu csp3 jp21 etch sw3 jp22 etch r21 1.0 c147 470pf l4 dnp dron v5_drmos l7 dnp vdc c277 1uf c39 0.1uf v5s place close to drmos pins c282 22uf c283 22uf c284 22uf c285 22uf ncp5338 u1 vin 11 vin 12 vin 13 vin 14 vswh 15 pgnd 16 pgnd 17 pgnd 18 pgnd 19 pgnd 20 vswh 31 vswh 32 vswh 33 vswh 34 vswh 35 gl 36 cgnd 37 disb# 39 pwm 40 zcd_en# 1 vcin 2 nc 3 boot 4 gh 6 phase 7 vin 9 vin 10 pgnd 21 pgnd 22 pgnd 23 pgnd 24 pgnd 25 pgnd 26 pgnd 27 pgnd 28 vswh 29 vswh 30 cgnd 5 cgnd 41 vin 42 vswh 43 vin 8 thwn 38 j132 gh2 r15 0.00 j117 c44 4.7uf c267 1uf r14 1.00 place caps close to drmos pins on top place close to drmos pins vdc smod2 sw2 csn2 vccu csp2 sw2 r7 1.0 jp17 etch c145 470pf jp18 etch l2 dnp dron v5_drmos pwm1 gl1 place close to drmos pins j133 ncp5338 u2 vin 11 vin 12 vin 13 vin 14 vswh 15 pgnd 16 pgnd 17 pgnd 18 pgnd 19 pgnd 20 vswh 31 vswh 32 vswh 33 vswh 34 vswh 35 gl 36 cgnd 37 disb# 39 pwm 40 zcd_en# 1 vcin 2 nc 3 boot 4 gh 6 phase 7 vin 9 vin 10 pgnd 21 pgnd 22 pgnd 23 pgnd 24 pgnd 25 pgnd 26 pgnd 27 pgnd 28 vswh 29 vswh 30 cgnd 5 cgnd 41 vin 42 vswh 43 vin 8 thwn 38 gh1 r16 0.00 j118 l6 dnp c50 4.7uf c268 1uf r18 1.00 place caps close to drmos pins on top place close to drmos pins sw1 csn1 smod1 vccu csp1 sw1 r8 1.0 jp19 etch c146 470pf jp20 etch l3 dnp dron v5_drmos l5 dnp vdc vdc c274 1uf c272 1uf c38 0.1uf v5s c37 0.1uf c280 22uf c281 22uf v5s
NCP81111 www. onsemi.com 6 absolute maximum ratings electrical information pin symbol v max v min i source i sink vff 30 v ?0.3 v n/a n/a vdig 3.3 v all other pins 6.5 v ?0.3 v n/a n/a *all signals referenced to gnd unless noted otherwise. thermal information description symbol typ unit thermal characteristic, qfn package (note 1) r ja 44 c/w operating junction temperature range (note 2) t j ?10 to 125 c operating ambient temperature range ?10 to 100 c maximum storage temperature range t stg ?40 to +150 c moisture sensitivity level qfn package msl 1 *the maximum package power dissipation must be observed. 1. jesd 51?5 (1s2p direct?attach method) with 0 lfm 2. jesd 51?7 (1s2p direct?attach method) with 0 lfm electrical characteristics unless otherwise stated: ?10 c < t a < 100 c; 4.75 v < v cc < 5.25 v; c vcc = 0.1 f parameter test conditions min typ max unit bias supply vcc quiescent current en = high 30 40 50 ma en = low 10 a ps3 40 ma vcca uvlo threshold vcc rising 4.4 4.55 v vcc falling 4.1 4.2 v vcca uvlo hysteresis 200 mv vdig uvlo threshold vdig rising 1.65 1.8 v vdig falling 1.27 1.45 v vdig uvlo hysteresis 200 mv enable input enable high input leakage current external 1k pull?up to 3.3 v 1.0 a upper threshold v upper 0.8 v lower threshold v lower 0.4 v total hysteresis v upper ? v lower 100 mv enable delay time measure time from enable transitioning hi to when dron goes high, vboot is not 0 v 1 ms differential voltage sense input bias current ?400 400 na vsp input voltage range ?0.3 3.0 v vsn input voltage range ?0.3 0.3 v
NCP81111 www. onsemi.com 7 electrical characteristics unless otherwise stated: ?10 c < t a < 100 c; 4.75 v < v cc < 5.25 v; c vcc = 0.1 f parameter unit max typ min test conditions drvon output high voltage sourcing 500 a 3.5 v output low voltage sinking 500 a 0.1 v rise/fall time cl (pcb) = 20 pf, vo = 10% to 90% 10 ns internal pull down resistance en = low 70 k iout monitor analog gain accuracy ?3% +3% analog gain range 16 1024 analog gain step size binary weigh ted analog iout offset accuracy gain = 64, csx sum = 40 mv, digital gain = 1 3 lsb digital gain step size digital gain is 2.8 format 0.4% digital gain range 0.004 4 adc voltage range 0 2.56 v adc total unadjusted error (tue) max % error of the ideal value ?1 +1 % adc differential nonlinearity (dnl) highest 8?bits 1 lsb adc conversion time 10 s adc conversion rate per channel 33 khz internal ramp ramp slope accuracy ?5 5 % ramp reset voltage step size 8 mv maximum ramp reset step 486 512 538 mv ramp slope maximum single phase mode 4000 mv/ s ramp slope minimum single phase mode 5.6 mv/ s ramp slope step size single phase mode typical 5.3 5.6 5.88 mv/ s output over voltage & under voltage protection (ovp & uvp) over voltage set point accuracy threshold is programmable ?20 20 mv over voltage max capability 3 v over voltage delay vsp(a) rising to pwmx low 400 ns under voltage threshold below dac?droop vsp(a) falling 415 450 475 mv under voltage hysteresis vsp(a) rising 100 mv under voltage delay 150 ns droop gain accuracy guaranteed by design ?2 +2 % programmable gain range csx sum to diffout 0,0.3 16.5 gain step size 1.2 % offset accuracy csx input referred from 1.0 v to 2.0 v ?2.5 2.5 mv common mode rejection csx input referred from 1.0 v to 2.0 v 60 80 db overcurrent protection ilim threshold accuracy sum of csx inputs ?3.5 3.5 mv
NCP81111 www. onsemi.com 8 electrical characteristics unless otherwise stated: ?10 c < t a < 100 c; 4.75 v < v cc < 5.25 v; c vcc = 0.1 f parameter unit max typ min test conditions overcurrent protection step size 2 mv maximum setting sum of csx inputs 126 mv ilim delay 1000 ns zcd comparator offset accuracy ?1.5 1.5 mv offset programmable range guaranteed by design ?6.2 6.2 mv offset step size guaranteed by design 0.2 mv vr_hot# output low resistance i_ vrhot = ?10 ma 13 output leakage current high impedance state ?1.0 1.0 a tsense temperature accuracy (0 c and 125 c) using murata thermistor ncp18wm224j03rb (220 k ) ?4 4 c internal resistance hot range 50 c to 125 c 9.8 11.5 13.2 k internal resistance cold range 0 c to 50 c 146 172.5 198 k bias current hot range 50 c to 125 c 49.3 58 66.7 a bias current cold range 0 c to 50 c 4.1 4.83 5.6 a 6 bit current share adc voltage range ?24 39 mv differential nonlinearity (dnl) 2 lsb step size 1 mv conversion time 550 ns common mode range 0.5 2.5 v vr_rdy (power good) output low saturation voltage i vr_rdy(a) = 4 ma, 0.3 v rise time external pull?up of 1 k to 3.3 v, c tot = 45 pf, vo = 10% to 90% 100 ns fall time external pull?up of 1 k to 3.3v, c tot = 45 pf, vo = 90% to 10% 10 ns output voltage at power?up vr_rdy pulled up to 5 v via 2 k 1.0 v output leakage current when high vr_rdy = 5.0 v ?1.0 1.0 a vr_rdy delay (rising) dac=target to vr_rdy 5 6 s vr_rdy delay (falling) uvp response time 5 s vr_rdy delay (falling) ocp response time 1000 ns vr_rdy delay (falling) ovp response time 250 ns vr_rdy delay (falling) setvid 0 v if register 34h is set to respond 500 ns vr_rdy delay (falling) time after enable transitions low 1.3 1.5 s pwm output high voltage no load vcc v output low voltage no load gnd v
NCP81111 www. onsemi.com 9 electrical characteristics unless otherwise stated: ?10 c < t a < 100 c; 4.75 v < v cc < 5.25 v; c vcc = 0.1 f parameter unit max typ min test conditions pwm rise and fall time cl (pcb) = 25 pf, vo = gnd to vcc 1 ns ton accuracy ?5 5 % ton step size 1.25 ns ton range 15 2559 ns smod output high voltage no load vcc v output low voltage no load gnd v rise and fall time cl (pcb) = 25 pf, vo = gnd to vcc 1 ns vff adc / vff uvlo note: uvlo threshold is programmable step size 200 mv maximum tracking slew rate 2.5 v/us maximum input 25.5 v general the NCP81111 is a single output three phase digital controller designed to meet the intel vr12.5 specifications with a serial svid control interface. the NCP81111 implements vr12.5 or vr12.6 depending on the device configuration.
NCP81111 www. onsemi.com 10 i2c user commands these commands operate on a subset range of address space and are primarily for use by end users during application configuration. user_reg_read this command can read one or more bytes from the working register set. the address (user_addr) specified with this command is a working set address from the user address range (refer to the user column in the register map). only registers which have read access (shown as (r) or (rw) in the user column) can be read with this command. if the command is specified with an address that does not have read access the device will respond with na (not?acknowledge). however, if a block of registers are read which start from a valid address, then via the auto?incrementing address point to an address that does not have read access, then for those invalid registers the return value will be 00h (zeros). the invalid registers do not stop the command, and the device will respond with an a (acknowledge). this allows a single user_reg_read command to read a contiguous block of d ata even if it spans addresses that are not valid. note that this command requires a repeated start sequence to change the data direction. also, for the final byte received by the master it must signal end of data to the device by responding with a na (not?acknowledge). this allows the device to release the data line so the master can send the stop sequence. if a long sequence of data is read, which due to the auto?incrementing address exceeds the allowable address range, then the device will return zero values (00h) for bytes beyond the address boundary. for a single?byte read the sequence is as follows: s i2c_addr+w a user_reg_read a user_addr a sr i2c_addr+r a d0 na p this will read the data from the working register map as shown: working registers data address d0 user_addr for a multi?byte read command the sequence is as follows: s i2c_addr+w a user_reg_read a user_addr a sr i2c_addr+r a d0 a d1 a d2 a ... na p this will read the data from the working registers as shown: working registers data address d0 user_addr d1 user_addr+1 d2 user_addr+2 ... ... user_reg_write this command will write one or more bytes into the working register set. the address (user_addr) specified with this command is a working set address from the user address range (refer to the user column in the register map). only registers which have write access (shown as (rw) in the user column) can be written with this command. if the command is specified with an address that does not have write access the device will respond with na (not?acknowledge). however, if a block of registers are written which start from a valid address, then via the auto?incrementing address point to an address that does not have write access, then for those invalid registers the input data will be ignored. the invalid registers do not stop the command, and the device will respond with an a (acknowledge). this allows a single user_reg_write command to write a contiguous block of data even if it spans addresses that are not valid. if a long sequence of data is written which exceeds the allowable address range then the command will automatically terminate when the end of the address range is reached. attempting to write past this point will result in na (not?acknowledge) responses from the device.
NCP81111 www. onsemi.com 11 for a single?byte write the sequence is as follows: s i2c_addr+w a user_reg_write a user_addr a d0 a p this will insert data into the register as shown: working registers data address d0 user_addr for a multi?byte write command the sequence is as follows: s i2c_addr+w a user_reg_write a user_addr a d0 a d1 a d2 a ... a p this will insert a block of data into the registers as shown: working registers data address d0 user_addr d1 user_addr+1 d2 user_addr+2 ... ... user_nvm_reload this command will reload the user nvm settings from the nvm into the working registers. the sequence is as follows: s i2c_addr+w a user_nvm_reload a p the command will reload all the registers at once and should complete in less than 50 s (worst case). this can be used to restore user settings after altering the working registers via the i2c interface. the reload is forced and does not require the settings to be configured. user_nvm_write this is the primary method for writing the user nvm settings into the nvm. the sequence is as follows: s i2c_addr+w a user_nvm_write a p the command will write all the current user settings from the working registers into the nvm. it should complete in less than 988 ms (worst case, 380 ms typical case). i2c user_power control due to the internal construction of the device, when the en pin goes low the internal regulators will turn off and the device will lose its working state. subsequently if the en pin goes high the device will reinitialize its state from the nvm configuration. for purposes of test and application configuration it is useful to power cycle the device without necessarily losing state. in addition, preserving state allows the device to optionally skip nvm load and/or auto?calibration sequences resulting in a faster startup time. to accomplish this, the user_power command was added which allows the user to enable/disable the device without power?cycling the part. it also allows the nvm, working registers, and auto?calibration behavior to be modified when exiting the disabled state. the key to this command is the concept of a ?virtual enable? signal. this virtual?en signal can be controlled via the user_power command and will behave in a similar way to the actual en?pin, however when the virtual?en is set low it will not complete ly power off the device. the internal regulators and clocks will continue running in order to preserve device state. note, the en?pin must remain high at all times when using the device in this way.
NCP81111 www. onsemi.com 12 the command sequence is as follows: s i2c_addr+w a user_power a power_setting a p where the power_setting byte is mapped as follows: power_setting: 0 0 0 reset_test reset_mem reset_autocal restart enable ? enable ? this bit is the ?virtual enable? signal. when the device is in the disabled state, sending the user_power command with this bit set to ?1? will cause the device to exit the disabled state and begin the power?up sequence. the exact power?up sequence followed will depend on the other bit settings. if the device is in an operational state (not disabled) and the command is issued with this bit set to ?0? then the device will stop operation and enter the disabled state. ? restart ? this bit is used in conjunction with the enable bit. it is used to immediately restart the device when the disabled state has been entered. so when the device is in an operational state, if the user_power command is issued with this bit set to ?1? and the enable bit set to ?0?, the device will stop operation, enter the disabled state, and then immediately power?up again. it is in essence a fast toggle on the virtual enable signal, used to quickly cycle the device through its power?up sequence. ? reset_autocal ? when this bit is set to ?1?, upon exiting the disabled state, the device will reset its auto?calibration state and proceed to recalibrate during power?up. normally auto?calibration is only required if the device has lost its state (thus it will occur anytime the actual en?pin is toggled), however the procedure takes a few milliseconds to complete. since the device can retain state using this command, if this bit is set to ?0?, the auto?calibration settings will be retained and the procedure will be skipped. a ?0? setting will allow the device to power?up several milliseconds faster than normal. ? reset_mem ? this bit controls the behavior of the working registers and the nvm during power?up. if the bit is set to ?1? then upon exiting the disabled state the working registers will be reinitialized ? first the por settings will be applied, then the nvm will be read and those settings will be applied. any changes to the working registers that were not programmed to the nvm will be lost. if the bit is instead set to ?0? then the device will retain all the settings that are currently in the working registers. a ?0? setting is useful for testing minor changes to device settings without needing to program them to nvm. ? reset_test ? if the bit is set to ?1? then upon exiting the disabled state, the test registers will be reset to their por defaults. a ?1? setting is useful for quickly clearing all test modes when cycling through a power?up sequence. if the bit is set to ?0? then the test registers will be unaffected by the power?up sequence. example command sequences: starting from a normal operational state, issuing the following command: s i2c_addr+w a user_power a 00000000b a p will cause the part to exit to the disabled state and remain there. the test interface can then be used to modify the working registers and adjust settings prior to re?enabling the part. starting from the disabled state, issuing the following command: s i2c_addr+w a user_power a 00000001b a p will cause the part to exit the disabled state and begin power?up. the working registers will not be affected during power?up, and auto?calibration will be skipped (note: this is only true if auto?cal has completed its sequence at least once. starting from any state, issuing the following command: s i2c_addr+w a user_power a 00000110b a p will cause the part to exit to the disabled state, then immediately begin power?up. the working registers will not be af fected during power?up, however the part will recalibrate. starting from any state, issuing the following command:
NCP81111 www. onsemi.com 13 s i2c_addr+w a user_power a 00011010b a p will cause the part to exit to the disabled state, then immediately power?up again. on power?up it will clear the test registers and reload the nvm into the working registers. it will skip the auto?calibration sequence. this is very similar to toggling the en?pin, but with a faster powerup time. starting from any state, issuing the following command: s i2c_addr+w a user_power a 00011110b a p will cause the part to exit to the disabled state, then immediately power?up again. on power?up the controller will clear the test registers and reload the nvm into the working registers. it will recalibrate during power?up. this is exactly the same as toggling the en?pin, but with a slightly faster power?up time (due to regulators and clocks already being powered up and running). device configuration the following sections describe the configuration of certain device register groups based on function. external address offset there is an external address offset circuit which can be used to allow otherwise identically programmed devices to be placed on a common bus. the address that the devices will respond to can be altered via an external resistor network. the address offs et circuit can offset both the i2c and svid addresses by an offset range of +0 to +15. the address system is controlled by the following registers: table 1. i2c / svid address registers register (i2c addr) r/w purpose description 43 bits<2:0> rw address offset configuration this register has bit flags as follows: 0 0 0 0 0 apply_svid_ addr_offset apply_i2c_ addr_offset en_addr_offset these bit flags control whether the external address offset function is enabled, and if so how the offset is applied. apply_svid_addr_offset = when set the address of fset will be applied to the svid address (default enabled) apply_i2c_addr_offset = when set, the address offset will be applied to the i2c address (default enabled) en_addr_offset = controls if the address offset circuit is enabled (default enabled) 50 bits<6:0> rw i2c address this settings holds the base i2c address. the value should be between 8 to 119. default is 68 (44h). 0?7 = invalid (i2c reserved) 8?119 = valid (08h ? 77h) 120?127 = invalid (i2c reserved) 51 bits<3:0> rw svid address this setting holds the base svid address. the value can be between 0 to 15 (0h ? fh). default is 0 (0h). the address offset circuit is enabled by default on an unprogrammed device. it can be disabled by writing a zero into en_addr_offset (register 43, bit 0) when programming the device. when enabled, the device will sense resistors attached to the test2 and test3 pins during powerup and will add the resulting offset to the svid and i2c base addresses as defined by the bit flag settings above. addresses that exceed the maximum address will wrap around. for instance: the address offset that is generated is determined by the resistors placed between the test2/test3 pins and gnd. the system uses 20 k increments per step, and both the highest and lowest settings will give an address offset of zero (this is to allow the test pins to be either shorted or open on a single?vr application or during device evaluation). the following tables list the resultant offsets versus resistance for the test2 and test3 pins. the individual offsets are added to give a total offset.
NCP81111 www. onsemi.com 14 table 2. test2 address offset address offset resistance (k ) 0 0?60 +8 80?140 0 >160 table 3. test3 address offset address offset resistance (k ) 0 0 +1 20 +2 40 +3 60 +4 80 +5 100 +6 120 +7 140 0 >160 the address offset value is latched during power?up as part of nvm initialization. it will be retained for the duration of device operation. enabling/disabling the device via user_power commands will not cause the address offset value to be relatched. the only way to relatch the address offset value is to either power cycle the device or use a user_power command with the reset_mem flag set. after power?up the resulting address offset value can be read via i2c (note: if i2c address offset is enabled, this requires knowing the offset in advance, if this is not the case, then the hardwired addressing mode can be used): table 4. address offset readback register (i2c addr) r/w purpose description 219 bits<3:0> r address offset readback of the latched address offset dac feed forward a dac feed forward (abbreviated dacff) function has been added to the device. the purpose of this circuit is to counteract the transient response of the output pole given by the droop resistance and the output load capacitance. in order to do this the dacff circuit adds a counteracting zero which cancels the pole. this is illustrated below, where z = = 1/rc, with r = droop resistance and c = output load capacitance:
NCP81111 www. onsemi.com 15 dac dacff vsp c r mag(db) 0 mag(db) 0 mag(db) 0 dacff(s) s z g(s) 1 s z h(s) 1 1 s vsp dac 1 s z 1 1 s 1 z 1 rc z 1 rc figure 5. there are some important things to note about the dacff system: ? this effect is only applied in the vid up direction, and allows the dac to closely follow the ideal ramp slope behavior. the effect is not applied in the vid down direction to prevent potential voltage undershoot. ? for the effect to work properly the internal dacff coefficients (given below) must be set properly with respect to the actual droop resistance and output load capacitance. improperly setting the coefficients may yield a lagging voltage response (under?compensated) or overshoot artifacts (over?compensated). for this reason the feature is disabled by default and must be explicitly enabled via end?user configuration. ? the above representation is a theoretical idealized model. in practice due to the digital nature and internal clock frequency of the vid controller an additional high?frequency pole is introduced. the actual transfer function of the dacff circuit is given below. from a transient perspective this pole will have an effect on the leading and trailing response of the dacff function (the transition from vid up to vid stable, or vice?versa), and it?s effect will be discussed more in the coefficient calculation section below. dacff(s) s z 1 s p (eq. 1) there are two dacff coefficients, a 16?bit a?coefficient and an 8?bit b?coefficient. they can be calculated with the following equations and procedure. a[15 : 0] 2 t z 1 2 t p 128 b[7 : 0] 2 t p 1 1 2 t p 256 (eq. 2) where: z 1 rc p 2 f p where f p 3.18 mhz
NCP81111 www. onsemi.com 16 t = 100 ns = 1 ? 10 ?7 r = droop resistance c = output load capacitance calculation procedure: 1. calculate z and choose initial p . use those parameters to calculate a/b?coefficients. 2. program the device with the coefficients, and enable the dacff function. observe the transient behavior. 3. adjust a/b?coef ficients directly as needed to modify the transient behavior as shown below. 4. program the new coefficients and iterate as needed until satisfactory transients are obtained. to the first?order the magnitude of the dacff function will be controlled by the a?coef ficient and the frequency response will be controlled by the b?coef ficient. this is illustrated below and can be used as a guideline when adjusting the coef ficients to obtain the desired response. vsp (dacff disabled) dac vsp (dacff enabled) a?coeff controls magnitude dac b?coeff controls speed of trailing?edge transient roll?off figure 6. iout gain programming the NCP81111 has a high accuracy 10 bit a/d to monitor the total output current. the iout gain and the iccmax register are user programmed and stored in the nonvolatile memory. the iout gain consists of two analog gain stages and one digital gain stage for fine gain adjustment. when setting the iout gain the user must be care not to exceed the maximum input a/d signal capability using the analog gain. set the digital gain to unity and then adjust the analog gain to get the maximum signa l into the a/d without exceeding ffh at iccmax load in the iout register. then fine tune the digital gain to achieve ffh in the iout register under the iccmax load condition. iout offset can be adjusted after the a/d conversion via register 84d. av=16 imon summing amp + csp1 + csp2 + csp3 ? csn1 ? csn2 ? csn3 csp csn av iout 2nd gain stage csp csn iout_p iout_n gain<> av iout 3d gain stage csp csn iout_p iout_n gain<> 10bit a/d in_p in_n out<9:0> 81d<1:0> 81d<2:3> 84d<7:0> iout<7:0> 82d<7:0> sum av 700hz digital adjust gain<7:0> out<7:0> offset<7:0> iout<9:0> figure 7. iout signal chain
NCP81111 www. onsemi.com 17 iout configuration table function register value stage2 iout gain stage3 iout gain 81d<1:0> 81d<3:2> 0: 1 1: 2 2: 4 3: 8 digital gain 82d<7:0> absolute 2.8 format (2 integer, 8 fractional), 0.00390625 per step example 100h = 256d gain = 1 iout offset ps0 84d<7:0> 2?s complement format imon offset ps1 115d<7:0> 2?s complement format imon offset ps23 116d<7:0> 2?s complement format imon settling time 110d<1:0> 99% settle in => 00b=840 s, 01b=1.68 ms, 10b=3.36 ms, 11b:6.72 ms the equation for iout tuning is as follows. 2.5 v g 1 g 2 dcr 0.75 g digital i cc_max (eq. 3) when tuning the iout analog gain g1 and g1 need to be set such that the iout is between 80h and ffh but the voltage at the a/d should not exceed 2.5v at icc_max or the iout signal will saturate the a/d converter. the offset can also be adjusted. a/d range ffh 80h icc_max analog gain target window digital gain =1 offset=0 figure 8. the internal offset of the iout signal chain is auto?calibrated and has very low offset. the current sense rc filter itself has some nonlinear behavior when using thick film resistors. this creates a positive offset on iout that can be observed to follow the input supply voltage, vout, and phase count. using physically larger thick film 0805 resistors or two 0603 resistors in ser ies can reduce but not eliminate this effect. the system provides the iout offset adjust registers to help compensate for this effe ct. for best performance using a metal film resistor is required in the cs filter network. ocp current limit programming the NCP81111 uses a latching total current limit function. if the current limit is exceeded the controller will tri?state the output stage. there is an adjustable filter speed for the ocp function. the filter can be disabled for the fastest response. th e ocp has three user settings to accommodate different current limits in separate power states. the current limit is a total current limit and is digitally programmable in 2 mv steps to a maximum of 126 mv referred to the total cs input sum. table 5. ocp configuration table function register value ocp ps0 85d<5:0> 2 mv per step 0d = 0 mv to 63d = 126 mv ocp ps1 86d<5:0> 2 mv per step 0d = 0 mv to 63d = 126 mv ocp ps23 87d<5:0> 2 mv per step 0d = 0 mv to 63d = 126 mv ocp filter bandwidth 85d<7:6> 00b:250 khz , 01b:125 khz, 10b:75 khz, 11b:50 khz ocp filter enable 86d<6> 0:use filter, 1:no filter
NCP81111 www. onsemi.com 18 compensator tuning the NCP81111 uses a hybrid compensator. the high frequency performance is provided by a 100 mhz bw op?amp. the digital integrator allows better control of the low frequency transient response. r1 and can be adjusted for power states ps0 and ps1,2,3 to optimize the loop gain based on the number of phases running. figure 9. hybrid compensator diagram + ? digital integrator sum vsp vsn dac gnd 1.3v 1.3v diffout 1.3v c1 r3 c2 r1 droop_p droop_n 50k 50k comp equation 4 ? compensator t ransfer function comp(s) diffout(s) ? ai gm 2 c cap divisor v ramp s 1 r3 1 c3 s 1 100k 1 r1 c2 s (eq. 4) analog compensation configuration table function register value r1 (ps0) r1 (ps123) 95d<3:0> 95d<7:4> 0:33k, 1:50k, 2:75k, 3:100k, 4:150k, 5:200k, 6:250k, 7:300k, 8:350k, 9:400k, 10:450k r3 96d<5:3> 0:10k, 1:20k, 2:30k, 3:40k, 4?7:50k c1 96d<2:0> 0:0pf, 1:1.23pf, 2:3.48pf, 3:8.02pf , 4:17.12pf, 5:35.8pf, 6?7:24.3pf c2 97d<2:0> 0:0ff, 1:185ff, 2:90ff,3:522ff ,4?7:1.373pf digital integrator the digital integrator allows for independent tuning of the load step and load release response time and allows the user to change the offset during power state changes to smooth the transition of the power state changes. the current dac step size controls the working range/ resolution of the digital integrator. gm osc up down divisor divisor counter + offset current dac step size 1.3v diffout power state step size figure 10. the digital integrator is a voltage to current function. the gm is approximately 180 s, vramp is ~50 mvm and ccap in the oscillator is 2 pf. the step size ai for the current dac is user adjustable. the digital integrator transfer function can be
NCP81111 www. onsemi.com 19 approximated with the following equation below . the current gain ai is the integrator current step multiplied by the size multiplier. i(s) verror(s) ai gm divisor v ramp c cap s (eq. 5) the digital integrator also includes a stop function that can be adjusted to improve some aspects of the dynamic response such as load release. if the output of the error amplifier falls below the integrator stop threshold the digital integrator cou nter will be stopped to limit the integrator windup effect. in some cases the range of the integrator is sufficient to stop the wind up effect. figure 11. example compensator gain transfer function with mismatched increment and decrement gains digital integrator configuration table function register value integrator step size multiplier integrator current step 88d:<7> 89d:<4:3> 0: 100% step size 1: 75% step size 0: 5na, 1:10na, 2:15na, 3:20na integrator decrement divisor ps0 ps1 ps23 90d<5:3> 91d<5:3> 92d<5:3> 0:1, 1:2, 2:4, 3:8, 4:16, 5:32, 6:64, 7:128 integrator increment divisor ps0 ps1 ps23 90d<2:0> 91d<2:0> 92d<2:0> 0:1, 1:2, 2:4, 3:8, 4:16, 5:32, 6:64, 7:128 integrator offset ps1 step 93d<7:0> 2?s compliment format integrator offset ps23 step 94d<7:0> 2?s compliment format integrator stop threshold ps0 ps1 ps23 88d<0:2> 88d<5:3> 89d<2:0> 0:0.90v, 1:0.95v, 2:1.00v, 3:1.05v, 4:1.10v, 5:1.15v, 6:1.20v, 7:1.25v phase shedding threshold when a power state command alters the phase count the controller will automatically reduce the current in the phases that are to be shed to the threshold level set by the user and then shutdown the phase. this allows the controller to minimize the voltage deviation during phase shedding operation.
NCP81111 www. onsemi.com 20 phase shed threshold configuration table function register value phase shed threshold 73d<5:0> lsb = 1 mv 2?s complement format vboot voltage programming the NCP81111 has a vboot voltage register that can be configured to any valid vid value. if vboot is configured to zero, the controller will wait for an initial svid voltage command to begin soft start. dac offset voltage programming the NCP81111 has a user fine trim for the output voltage that is adjustable for each power state. zdc offset programming the NCP81111 is optimized to work with the on?s hfvr high performance drmos drive stage. the zcd detector is located in the controller and the offset is adjustable for optimization by the user. this allows for timing variations in the design zcd offset configuration table function register value zdc offset trim 114d<5:0> 0.2 mv per lsb sign magnitude format. vff under - voltage protection programming the controller is protected against under?voltage on the vff input pin. the threshold is user programmable. vff under?voltage configuration table function register value vff uvlo threshold 93d<6:0> 200 mv per lsb example 14h = 4.0 v programming the phase count the phase count must be configured buy the user and stored in nvm before enabling the output. phase count configuration table function register value vr phase count 64d<7:6> 1: 1phase 2: 2phase 3: 3phase programming the minimum on, minimum off , and smod skew timing the controller is designed to guarantee the timing in certain cases to protect the gate driver from very rapid signal changes that could potentially result is shoot though of the power stage. the user may select the setting for this based on the application selection of the power stage. the recommended values for the hfvr drmos are noted in the table. minimum on and off time and smod skew configuration table function register value minimum on time phases 1 65d<5:0> minimum on time 1.25 ns per lsb example 1ah = 32.5 ns minimum on time phases 2 and 3 64d<5:0> minimum on time 1.25 ns per lsb example 1ah = 32.5 ns minimum off time 66d<4:0> lsb = 2.5 ns example 0dh = 32.5 ns smod skew time 69d<4:0> lsb = 2.5 ns example 06h = 15 ns programming the period of operation the NCP81111 is designed to maintain a constant frequency in as many operating cases as possible. the on time of the controller varies based on many factors including vid setting, input voltage feed forward, load and power state. the frequency in continuous mode operations is controlled by the user period setting. under some conditions including low vid and high vin the frequency of operation may reduce due to reaching the minimum on time limits. the period setting is based on the
NCP81111 www. onsemi.com 21 individual phase frequency desired. example 134h = 770 ns for 1.3 mhz for this case the registers would be configured as follows. 72d = 34h with 73d<3:0> = 001b. period configuration table function register value user period low byte 71d<7:0> 2.5 ns per lsb user period high byte 72d<3:0> programming the boost cap functions due to the high voltage operation of the output under some conditions the gate driver floating boost cap voltage may discharge to unacceptable levels, this is especially likely to occur when using 5 v gate drivers. the NCP81111 has several functions to maintain the charge on the boost capacitors such that the gate driver is ready to use when needed. these timers are user adjustable for custom optimization. the tboost period sets the time between recharge events for the phases that are shed. the tboost time sets the amount of time the switch node is pulled low to charge the boost cap. the boost loop count is used at soft?start and sets the number of times the boost cap is charged before soft?start occurs. boost cap configuration table function register value tboost period 67<7:4> default 1h = 81.92 s tboost time 68d<7:0> 2.5 ns per lsb default 33h = 127.5 ns boost loop count 70d<3:0> default 8h for 8 loops. programming the ramp function the ramp signal is user adjustable. this allows the user to maximize the performance of the controller. the ramp provides a synchronization function for the controller and stabilizes the loop gain as well as the phase angles. the ramp has a reset vo ltage for each phase and the slope automatically adjusts for the phase count during phase shedding. to achieve a wide verity of accurate settings both the current and the ramp capacitor are adjustable. the adjustable ramp reset voltage allow for fine tuning of the phase angles if the ripple feedback is not well balanced. the ramp descends to 1.3 v and remains there until reset again . use the equation i = cdv/dt the ramp current setting is based on single phase ramp operation. figure x shows how to select the ramp cap and ramp slope. the design should target the trigger point near 1.31 v just above were the ramp goes flat at 1.3 v . if the ramp intersects comp at high levels the load release response will be less aggressive and transitions into and out of dc m mode operation will be less smooth. if the ramp is too steep the comp will trigger on a flat ramp and the system will be less stable. figure 12.
NCP81111 www. onsemi.com 22 figure 13. multiphase ramp function modulator gain analysis the NCP81111 modulator has an inherent non?linear transient response that varies depending on the ramp settings. the small signal modulator gain can be found by taking the derivative of the non linear curve at the operating point. the result is the equation for am. a m : mc ton n vreset comp opp mc treset 2 comp opp : mc ton d n vreset n mc treset ?n (eq. 6) 0 0.05 0.1 0.15 0.2 0 0.2 0.4 0.6 0.8 dcomp () a m comp comp opp () dcomp opp () + comp figure 14. modulator gain function ramp configuration table function register value ramp cap setting 77d<3:0> 0: 0 pf 1: 1 pf 2: 2 pf 3: 3 pf 4: 4 pf 5: 5 pf 6: 6 pf 7: 7 pf 8: 8 pf 9: 9 pf 10: 10 pf 11: 11 pf 12 - 15: 12 pf ramp current setting 78d<7:0> 0 to 4.2291 ua 33.3 na per lsb phase 1 reset voltage 74d<7:0> 4 mv per lsb example 3fh = 63d = 1.556 v phase 2 reset voltage 75d<7:0> 4 mv per lsb
NCP81111 www. onsemi.com 23 ramp configuration table function value register phase 3 reset voltage 76d<7:0> 4 mv per lsb ramp reset time
NCP81111 www. onsemi.com 24 control loop analysis the ncp8111 control loop diagram can be modeled as shown below. the NCP81111 system is best described as voltage mode control with avp. avp does create a current feedback loop but the compensation signal does not directly control the current. figure 15. NCP81111 control loop figure 16. current loop closed using the test ports for debug this controller has dedicated test ports for monitoring internal signals for debug purposes. some of the more useful settings include a ccess to the internal droop, iout, and comp signals. the test pins have some impedance. for proper monitoring please use 1 m q or higher impedance probes. analog application notes section remote sense amplifier a high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of the regulator. the vsp and vsn inputs should be connected to the regulator?s output voltage sense points. differential current feedback amplifiers each phase has a low offset differential amplifier to sense that phase current for current balance. resistor rcsn must be 14 k to work correctly with the internal thermal compensation. it is also recommended that the voltage sense element be no less than 0.5 m for accurate current monitor and balance. the internal cs pin resistance forms a divider with the external cs filter resistor. only 14 k may be used for the external resistor. fine tuning of the cs filter must be done by adjusting the capacitor values. two parallel capacitors should be placed on each phase to allow for fine tuning of the time constant of the cs filter. the effective r in the rc time constant calculation will always be 10 k . select the c based on the l/(dcr * 10k) = ccsn. the internal thermal compensation resistor attenuates the signal from the inductor dcr. the thermal gain is approximately 0.75 at 25c for the inductor current sensing inputs. when calculating the droop gain the thermal gain effect must be included. for best droop and imon of fset performance rcsn should be of the metal film type resistor. using a lar ger thick film 14 k 0805 case size or two thick film 0603 case size resistors in series can offer improved current sense offset performance over a standard 0603 case size. equation 7 ? initial estimate equation for ccs total l dcr 10k ccs_total (eq. 7)
NCP81111 www. onsemi.com 25 drmos swn csp csn rcs =14 k ccs 1 vout rinternal ccs 2 rhf =10 chf =100 pf dcr l figure 17. phase current sense network tsense one temperature sense input is provided which monitors both vr_hot and inductor temperature for thermal compensation. a precision current is sourced out the output of the tsense pin to generate a voltage on the temperature sense network. there are two internal networks that connect to the ntc depending on the measured temperature to extend the accuracy of the thermal measurement across a greater temperature range. the ho t and cold range limits are controlled by the internal user registers. the voltage on the temperature sense input is sampled by the internal a/d converter and then digitally converted to temperature and stored in svid register. a 220k ntc similar to the murata ncp18wm224j03rb should be used. tsense internal ic a/d 11 .5k 172.5k 58ua 4.83ua hot cold 220k ntc place by phase 1 inductor board 3x figure 18. thermal sense diagram equation 8 ? tsense voltage calculation v adc 3 i bias r ntc r internal r ntc r internal (eq. 8)
NCP81111 www. onsemi.com 26 a/d result bias current temp_adc_hot temp_adc_cold 58ua 4.38ua figure 19. thermal bias current selection function the onboard a/d converter has 10 bits and the maximum dac voltage is 2.56 v with 2.5 mv per step. the user enters two constants 1/m and c for both the thermal ranges this adjusts the temperature calculation reported for the temperature registers and for vr_hot activation. c has an offset effect and m adjusts a slope ef fect. this allows the user to adjust the thermal gain . the conversion equation form the adc result to the reported temperature is shown below. equation 9 ? a/d t emperature conversion equation temperature c result adc m c 3 v tsense m (eq. 9) figure 20. example results of the thermal sense circuit tsense configuration table function register notes temp_adc_cold_low 100d<7:0> default value = deh = 222d => 57c temp_adc_cold_high 101d<1:0> default value = 0h temp_adc_hot_low 105d<7:0> default value = a2h temp_adc_hot_high 106d<1:0> default value = 2h 2a2h = 674 => 54c temp_inv_m_cold 102d<7:0> 1/m used for the cold range temperature calculation. default value = 18h = 24d temp_inv_m_hot 107d<1:0> 1/m used for the hot range temperature calculation. default value = 28h = 40d temp_c_cold_low 103d<7:0> default value = 3ch temp_c_cold_high 104d<1:0> default value = 03h note 33ch = 828d temp_c_hot_low 108d<7:0> default value = fdh temp_c_hot_high 109d<1:0> default value= 03h note 3fdh = 1021d
NCP81111 www. onsemi.com 27 vr_hot operation the vr_hot thresholds are controlled by the user setting for the temp max register. calculate the voltage thresholds on the tsense pin using the user settings for c and 1/m . see the equations below. tsense_vr_hot_assert_threshold c hot m hot temp_max 2.56 v 10243 (eq. 10) tsense_vr_hot_deassert_threshold
c hot m hot ( temp_thermalert ) 2.56 v 10243 (eq. 11) temp_max configuration table function register notes vr_temp_max 18d<7:0> 1degc per lsb input under - voltage protection under voltage protection under voltage protection will shut off the output similar to ocp to protect against short circuits. the threshold is specified in the parametric spec tables and is not adjustable. the controller is protected against under?voltage on the vcc and vff pins. function register notes disable_vff_uvlo 52d<2> 0:vff uvlo enabled 1: vff uvlo disabled vff_threshold 98d<6:0> lsb = 200 mv default = 0 assigning unused pwm and cs pins when using lower phase count arrangements always connect unused csn and csp pins together and to the nearest csn signal. unused pwm pins should be left floating. phase count pwm1 pwm2 pwm3 csp1 csn1 csp2 csn2 csp3 csn3 3 used used used used used used used used used 2 used used no connect used used used used connect to csn2 connect to csn2 1 used no connect no connect used used connect to csn1 connect to csn1 connect to csn1 connect to csn1 layout notes the NCP81111 has differential voltage and current monitoring. this improves signal integrity and reduces noise issues related to layout for easy design use. to insure proper function there are some general rules to follow. always place the inductor current sense rc filters as close to the csn and csp pins on the controller as possible. place the v cc decoupling caps as close as possible to the controller vcc pin.
NCP81111 www. onsemi.com 28 package dimensions qfn32 5x5, 0.5p case 485ce issue o seating note 4 k 0.15 c (a3) a a1 d2 b 1 17 32 e2 32x 8 24 l 32x bottom view top view side view d a b e 0.15 c pin one reference 0.10 c 0.08 c c 25 e notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min max millimeters a 0.80 1.00 a1 ??? 0.05 a3 0.20 ref b 0.20 0.30 d 5.00 bsc d2 3.40 3.60 e 5.00 bsc e2 e 0.50 bsc l 0.30 0.50 3.40 3.60 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 3.70 0.30 3.70 32x 0.62 32x 5.30 5.30 note 3 dimensions: millimeters l1 detail a l alternate constructions l ?? ?? a-b m 0.10 b c m 0.05 c k 0.20 ??? l1 ??? 0.15 pitch recommended NCP81111/d intel is a registered trademark of intel corporation in the u.s. and/or other countries. on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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